From my understanding, most modern consumer CPU's are based on synchronous logic. Some high-speed applications (signal processing, etc.) use ansync logic for its higher speed.

However, in today's market, speed in consumer products is one of the main selling points (see AMD vs Intel.) Is the development of more complicated lithography faster than adoption of fully asynchronous logic? Or is ansync logic too complicated/impractical for VLSI applications?

I spent some years in a startup commercialising async design technology, so I'm familiar with the reasons:

• async isn't intrinsically faster. The worst-case path delay remains the same. It's just that sometimes you get to take advantage of a faster path executing.




• async has overhead of completion detection too.




• Design tools. This is the really big one: there isn't really a full async "flow" of tools available to the same quality as synchronous design.




• Training. You'd effectively have to retrain all your designers on the new paradigm and tools.




• Risk and conservativism. So much of the industry is "produce something similar to the last one, but a bit different". This has a very high chance of working. Companies are much more reluctant to build something totally different since it has much more chance of being a total writeoff costing tens of millions of dollars.

It is very tempting to design asynchronous integrated circuits. The other answers already cover many reasons to think twice before doing it. Here is one more:

IC development is not finished with the design. Verification and test are equally important. Not only the design tools are very advanced for synchronous circuits, but it is the same with simulation tools and test equipment.

Verification

It is not sufficient to have the circuits working at lab conditions. They need to be robust with respect to the operating voltage (V) range, the operating temperature (T) range, and the variation due to the manufacturing process (P). For synchronous logic this can be guaranteed with the help of static timing analysis. The circuit is broken down to all timing paths, from flip-flop to flip-flop. Setup and hold times are checked for every single timing path, and for different combinations of P, T, and V. These PTV combinations are the so called simulation corners.

A similar verification could be done for asynchronous circuits, but it is much more difficult and much less supported by the design tools. It also restricts the designer to asynchronous constructs that actually can be verified. There is no reliable verification for arbitrary asynchronous circuits.

Test

Similar difficulties are there when it comes to testing the hardware. Testing synchronous logic is fully supported by testing standards and equipment. Testing asynchronous circuits not only is more complicated, but because of the lack of timing abstraction, it is not even sufficient to prove that the circuit will work for all PTV corners. The circuit could fail due to race conditions at some PTV combination, that is not covered by the corners.

Summary

IC designers have not given up the asynchronous paradigm, but asynchronous logic comes with heavy disadvantages during verification and validation. In an industrial context, asynchronous IC design needs to be restricted to construct that can be proven to work over the whole parameter space of process variation, as well as the operating ranges for temperature and voltage.

The so called "Locally synchronous globally asynchronous" design is one way to get more benefits and less disadvantages of both timing paradigms.

Async binary counters are simpler because they only use 1 memory cell or T flip flop per divide by two. Hence the old CD and 74HC4020 and 4040 offer many binary stages cheaply. The prop delay in each stage means it cannot be used without race conditions or glitches with gate decoding of the binary addresses unless the prop delay is less than 1/2 input clock cycle using the trailing edge to latch the result. The output latency is then multiplied by N stages.

Synchronous binary counters use an extra memory cell to D FF to delay but minimize the delay to 1 value for any length of counters so it consumes more area.

Hence all CPU’s use complementary clocks to optimize expected latency in address and memory read /writes to maximize thruput but not exceed prop delay, setup and hold times.

Memory now uses many phases such as DDR, 3DR, 4DR, 5DR especially for graphics memory but with CPU clocks going much faster than the single cycle RAM rate so that read and write address delays may be timed by single or multiple or half counts of the superclock ( eg 100MHz xN) designated by T fractional or integers counts for each parameter. These prop delays increase with temp. For CMOS and reduce with higher Vram voltage which if properly cooled might reduce latency or other increase Pd and temp rise and make it worse (slower). So cooling, V, f, T all are critical for optimal latency whether it is used for Async or Sync operations.

Early logic designs were asynchronous. Often times they were mixed with analog circuits too. However, as time progressed designs became more complicated, thus demanding more engineers to work on a single design. The timing diagrams of async. logic can be cumbersome when there are a lot of states. Now add a team of engineers trying to interface different blocks of logic together but the timings between them are not aligned very well. The designs become brittle to changes in unforeseen ways.

Enter synchronous logic design. Now all the state flows are aligned to a clock signal that allows the interfaces to be very well defined, and more robust against design changes. Yes, it might use more gates, but it is (usually) stable by design; as opposed to stable as long as no one touches it!