8:1 multiplexer to 6:1 multiplexer












4














I have 6 inputs that I want to insert in a 8-1 multiplexer. I just want to know how to modify the 8-1 mux to support only 6 inputs. I mean the last two rows on the truth table of the 8-1 won't be available.



This is the 8-1 mux I am using:
enter image description here



and its logic table:



enter image description here



I only want to use the D0 to D5 inputs.










share|improve this question
























  • Then ensure that your selection inputs only produces numbers in the range 000 to 101. Go stufy modulo arithmetic.
    – Andy aka
    Dec 12 at 15:36








  • 1




    You might tie the top 3 inputs together, thus 101,110, and 111 produce the same output. Will this confuse your state machine?
    – analogsystemsrf
    Dec 12 at 15:49






  • 2




    Nothing in the MUX should be modified. It's the S-inputs who define. The S>=6 should be don't cares.
    – Eugene Sh.
    Dec 12 at 15:50












  • Instead of placing the enable on the inputs, perhaps you should put the enable on the output? Literally after the OR gate and before it forks into Y and Ỹ. Besides, are you sure that it is Y and Ỹ, shouldn't they be swapped?
    – Harry Svensson
    Dec 12 at 18:27
















4














I have 6 inputs that I want to insert in a 8-1 multiplexer. I just want to know how to modify the 8-1 mux to support only 6 inputs. I mean the last two rows on the truth table of the 8-1 won't be available.



This is the 8-1 mux I am using:
enter image description here



and its logic table:



enter image description here



I only want to use the D0 to D5 inputs.










share|improve this question
























  • Then ensure that your selection inputs only produces numbers in the range 000 to 101. Go stufy modulo arithmetic.
    – Andy aka
    Dec 12 at 15:36








  • 1




    You might tie the top 3 inputs together, thus 101,110, and 111 produce the same output. Will this confuse your state machine?
    – analogsystemsrf
    Dec 12 at 15:49






  • 2




    Nothing in the MUX should be modified. It's the S-inputs who define. The S>=6 should be don't cares.
    – Eugene Sh.
    Dec 12 at 15:50












  • Instead of placing the enable on the inputs, perhaps you should put the enable on the output? Literally after the OR gate and before it forks into Y and Ỹ. Besides, are you sure that it is Y and Ỹ, shouldn't they be swapped?
    – Harry Svensson
    Dec 12 at 18:27














4












4








4







I have 6 inputs that I want to insert in a 8-1 multiplexer. I just want to know how to modify the 8-1 mux to support only 6 inputs. I mean the last two rows on the truth table of the 8-1 won't be available.



This is the 8-1 mux I am using:
enter image description here



and its logic table:



enter image description here



I only want to use the D0 to D5 inputs.










share|improve this question















I have 6 inputs that I want to insert in a 8-1 multiplexer. I just want to know how to modify the 8-1 mux to support only 6 inputs. I mean the last two rows on the truth table of the 8-1 won't be available.



This is the 8-1 mux I am using:
enter image description here



and its logic table:



enter image description here



I only want to use the D0 to D5 inputs.







multiplexer






share|improve this question















share|improve this question













share|improve this question




share|improve this question








edited Dec 12 at 18:21









mike65535

1,0001619




1,0001619










asked Dec 12 at 15:27









zaiz2s

211




211












  • Then ensure that your selection inputs only produces numbers in the range 000 to 101. Go stufy modulo arithmetic.
    – Andy aka
    Dec 12 at 15:36








  • 1




    You might tie the top 3 inputs together, thus 101,110, and 111 produce the same output. Will this confuse your state machine?
    – analogsystemsrf
    Dec 12 at 15:49






  • 2




    Nothing in the MUX should be modified. It's the S-inputs who define. The S>=6 should be don't cares.
    – Eugene Sh.
    Dec 12 at 15:50












  • Instead of placing the enable on the inputs, perhaps you should put the enable on the output? Literally after the OR gate and before it forks into Y and Ỹ. Besides, are you sure that it is Y and Ỹ, shouldn't they be swapped?
    – Harry Svensson
    Dec 12 at 18:27


















  • Then ensure that your selection inputs only produces numbers in the range 000 to 101. Go stufy modulo arithmetic.
    – Andy aka
    Dec 12 at 15:36








  • 1




    You might tie the top 3 inputs together, thus 101,110, and 111 produce the same output. Will this confuse your state machine?
    – analogsystemsrf
    Dec 12 at 15:49






  • 2




    Nothing in the MUX should be modified. It's the S-inputs who define. The S>=6 should be don't cares.
    – Eugene Sh.
    Dec 12 at 15:50












  • Instead of placing the enable on the inputs, perhaps you should put the enable on the output? Literally after the OR gate and before it forks into Y and Ỹ. Besides, are you sure that it is Y and Ỹ, shouldn't they be swapped?
    – Harry Svensson
    Dec 12 at 18:27
















Then ensure that your selection inputs only produces numbers in the range 000 to 101. Go stufy modulo arithmetic.
– Andy aka
Dec 12 at 15:36






Then ensure that your selection inputs only produces numbers in the range 000 to 101. Go stufy modulo arithmetic.
– Andy aka
Dec 12 at 15:36






1




1




You might tie the top 3 inputs together, thus 101,110, and 111 produce the same output. Will this confuse your state machine?
– analogsystemsrf
Dec 12 at 15:49




You might tie the top 3 inputs together, thus 101,110, and 111 produce the same output. Will this confuse your state machine?
– analogsystemsrf
Dec 12 at 15:49




2




2




Nothing in the MUX should be modified. It's the S-inputs who define. The S>=6 should be don't cares.
– Eugene Sh.
Dec 12 at 15:50






Nothing in the MUX should be modified. It's the S-inputs who define. The S>=6 should be don't cares.
– Eugene Sh.
Dec 12 at 15:50














Instead of placing the enable on the inputs, perhaps you should put the enable on the output? Literally after the OR gate and before it forks into Y and Ỹ. Besides, are you sure that it is Y and Ỹ, shouldn't they be swapped?
– Harry Svensson
Dec 12 at 18:27




Instead of placing the enable on the inputs, perhaps you should put the enable on the output? Literally after the OR gate and before it forks into Y and Ỹ. Besides, are you sure that it is Y and Ỹ, shouldn't they be swapped?
– Harry Svensson
Dec 12 at 18:27










1 Answer
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6














Assume that D6 and D7 are always low. Trace those signals through the gates in your design. If you find gates whose output values must always be the same, those gates can be removed and their output signals changed to a direct connection to logic '1' or '0'. Repeat until no gates are removed. Then remove unnecessary direct connections to logic '1' or '0'.






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    6














    Assume that D6 and D7 are always low. Trace those signals through the gates in your design. If you find gates whose output values must always be the same, those gates can be removed and their output signals changed to a direct connection to logic '1' or '0'. Repeat until no gates are removed. Then remove unnecessary direct connections to logic '1' or '0'.






    share|improve this answer


























      6














      Assume that D6 and D7 are always low. Trace those signals through the gates in your design. If you find gates whose output values must always be the same, those gates can be removed and their output signals changed to a direct connection to logic '1' or '0'. Repeat until no gates are removed. Then remove unnecessary direct connections to logic '1' or '0'.






      share|improve this answer
























        6












        6








        6






        Assume that D6 and D7 are always low. Trace those signals through the gates in your design. If you find gates whose output values must always be the same, those gates can be removed and their output signals changed to a direct connection to logic '1' or '0'. Repeat until no gates are removed. Then remove unnecessary direct connections to logic '1' or '0'.






        share|improve this answer












        Assume that D6 and D7 are always low. Trace those signals through the gates in your design. If you find gates whose output values must always be the same, those gates can be removed and their output signals changed to a direct connection to logic '1' or '0'. Repeat until no gates are removed. Then remove unnecessary direct connections to logic '1' or '0'.







        share|improve this answer












        share|improve this answer



        share|improve this answer










        answered Dec 12 at 15:33









        Elliot Alderson

        4,6651918




        4,6651918






























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